Build silicon that exists because your model needs it to.
We're an early-stage technical team solving a hardware specialization problem that affects every production ML organization. Six engineers covering the full stack from RTL to ML runtime, actively expanding. If the inference bottleneck problem is what you think about, we should talk.
Current openings.
You'll design and verify RTL for compute and control subsystems in the PCU-1 inference accelerator. Working closely with the physical design and compiler teams, you'll own modules from specification through synthesis and timing closure.
- 3+ years SystemVerilog or VHDL design experience for ASIC (not FPGA)
- Experience with formal verification tools (Cadence JasperGold, Synopsys VC Formal)
- Solid understanding of clock domain crossing and reset strategies
- Experience with synthesis and static timing analysis
- Background in ML accelerator architecture or memory subsystem design
- Familiarity with MLIR or low-level ML compute frameworks
You'll work on the graph compiler pipeline that ingests frozen ML models (ONNX, TensorFlow SavedModel, PyTorch export) and generates optimized dataflow programs for PCU-1 silicon. This is deep compiler work — graph partitioning, operator fusion, and target-specific code generation.
- Experience with MLIR, LLVM, or similar compiler infrastructure
- Solid background in ML computation graphs and common op semantics (matmul, attention, conv)
- Understanding of hardware architecture tradeoffs as they affect compiler decisions
- Python + C++ fluency
- Prior experience targeting custom accelerator backends
- Contributions to open-source ML frameworks or compiler projects
You'll build and operate the infrastructure for customer evaluation workloads — including model ingestion, batch job scheduling, and performance profiling pipelines. You'll work closely with evaluation customers on workload analysis and be the primary interface for technical onboarding.
- 3+ years production ML infrastructure experience (not training — inference)
- Proficiency with container orchestration and GPU cluster management
- Experience with latency/throughput profiling at infrastructure level
- Comfortable with Python and infrastructure-as-code tooling
You'll work on floorplanning, placement, routing, and signoff for the PCU-1 physical implementation. Working with advanced process nodes (targeting 7nm), you'll be responsible for achieving our power, performance, and area targets through physical optimization.
- 5+ years ASIC physical design experience, advanced node preferred
- Cadence Innovus or Synopsys IC Compiler II proficiency
- Experience with power intent (CPF/UPF) and low-power design techniques
- Familiarity with DRC/LVS sign-off flows
Engineering culture at an ASIC startup.
We focus on a specific problem — inference hardware specialization — and don't spread thin. Engineers have long uninterrupted time to do hard technical work.
You'll work with evaluation customers running production-scale models. Your compiler and silicon decisions get tested against real inference loads, not synthetic benchmarks.
Silicon and software engineers share context constantly. If you've ever wanted to understand how your compiler decisions land on actual transistors — or how hardware topology constrains your ML graph — this is the team.
Don't see a perfect match? Write us anyway.
We review all engineering applications. If your background is in silicon or ML systems, we'd like to hear from you.
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